Jitter Components

Jitter Components

The recent improvement to semiconductor device performance has seen bit rates of 28 Gbps become commonplace.  When using high-speed signals like the  28 Gbps band, the impact of jitter components from various sources in the surrounding environment on the transmission quality cannot be ignored. As a result, accurate evaluation of device characteristics requires testing by injecting multiple types of jitter on the device under test (DUT). Previously, jitter tolerance tests for the optical market required only applying of sinusoidal jitter  (SJ).  More recently, applying just SJ has caused difficulties in performing the accurate evaluation of device characteristics including the impact of the surrounding environment. This Application Note explains each type of jitter, gives some guidance about measurements for complex jitter tests and describes some concrete examples of jitter tolerance measurements using the Anritsu MP1900A.

Definition of Jitter Component Types

• SJ (Sinusoidal Jitter)

Sinusoidal Jitter is jitter with a single frequency component; it is the most basic jitter component of jitter tolerance tests. There is various jitter frequency components in the natural world and SJ is used for confirming the jitter tolerance at each frequency.

In transmission methods where the Data and Clock are not transmitted in parallel,  the Data signal generated from the transmitting device is retimed by the Clock Recovery circuit at the receiving device. The jitter tolerance characteristics are a key index in evaluating this re-timing operation. Generally, Clock Recovery uses an internal Phase Locked Loop (PLL) circuit. Figure 2.1.1 shows a Clock Recovery circuit.

Similar to a basic PLL circuit, the Clock Recovery circuit determines the Loop Bandwidth (Figure 2.1.2). When the Loop Bandwidth is wide, the jitter tolerance is excellent; a shorter Clock Recovery circuit lock time has merits but on the other hand, it increases the amount of carrier jitter in circuits downstream of the Clock Recovery. If the Clock Recovery lock time is short so as to recover the normal signal status, only a short time is required until the entire system recovers normal operation when the signal input to the Clock Recovery is lost or when the frequency has slipped momentarily.  Although a wide loop band achieves this short lock time, a disadvantage is that jitter in the input clock is easily transferred to circuits downstream of the Clock Recovery. For example, stacking-up several wide Loop Bandwidth Clock Recovery circuits may cause jitter summing in subsequent stages, risking incorrect operation of the entire system.

At a jitter tolerance test, it is important to confirm that the Loop Bandwidth of the above-described PLL is in accordance with the design and the degree to which it varies; as already described, the Clock Recovery has its own unique Loop Bandwidth. When the input Data signal jitter frequency and amount are within the Loop Bandwidth, an error does not occur due to a phase mismatch because recovered clock tracks input Data signal in terms of jitter. In other words, for the input Data and recovered Clock to have the same amount jitter, the relationship between the Clock and Data at D-FF  in  Figure  2.1.1 must be maintained so that no errors occur.

However, when the jitter in the input signal is out-of-band, the recovered Clock jitter is suppressed to be smaller than the jitter in the input Data signal. As a result, the relationship between the Clock and Data at D-FF in Figure 2.1.1 is changed and an error occurs. SJ is the most basic jitter component used at the jitter tolerance test for confirming the performance

limits caused by errors by changing the modulation frequency and amount in this manner. In addition, the jitter tolerance test for PCI Express specifies applying two SJs; the MP1900A supports either one or independent two SJs addition using option configurations.

Moreover, it can apply sufficient SJ of 1UI at jitter tolerance tests in the high-speed modulation area for modulation frequencies above 10 MHz.

• RJ (Random Jitter)

Random Jitter is a jitter component that is generated by noise effects that have no dependent relationship with frequency, such as thermal noise commonly occurring within systems, and it covers a wide frequency range.

For RJ, the CEI 3.0 jitter tolerance test standardizes the use of a High Pass Filter (HPF) to remove RJ components within the PLL band as shown below and applies only PLL out-of-band components as the load.

Using this standard, the HPF is set for frequency components below 10 MHz but it is necessary to apply frequency components at least exceeding the CDR bandwidth. The maximum amount of applied RJ is half the Baud rate so if the Baud rate is 28 Gbps, the applied RJ max. is 14 GHz. However, the actual CDR bandwidth does not extend to half the Baud rate, and it is usually sufficient to test a range of about 10 times the normal PLL bandwidth. Consequently, if the measuring instrument RJ band is from 100 to 200 MHz, the range required by the test will be sufficiently covered. As described in item 2.1 above, this is because jitter accumulates as the CDR bandwidth becomes wider, causing overall system instability.

The MP1900A has a built-in HPF and LPF for easy RJ injection. The built-in HPF and LPF should be used in combination to increase the reproducibility of jitter tolerance tests instead of attaching external filters. Additionally, RJ has an MP1900A Filter setting item; when PCIe is selected at Filter, the amounts of RJ (ps rms) for the Low and High-Frequency bands required by PCI Express can be set independently.

• BUJ (Bounded Uncorrelated Jitter)

Bounded Uncorrelated Jitter is generally jitter caused by crosstalk caused by nearby Data signals. When it is generated from a measuring instrument, a PRBS signal generated from an independent clock source that is unaffected by correlation from Data signals is used as the measurement target. If a PRBS15 signal is used as the measured Data signal, it is better to use something other than PRBS15 to avoid interference.

Moreover, it is best to set a value that is a multiple of the measured target bit rate to suppress interference even at the BUJ PRBS bit rate. The CEI 3.1 standard recommends using PRBS31 as a general test pattern as well as for jitter tolerance tests using measured target Data signals. The BUJ PRBS patterns are from 7 to 11 stages with baud rates of 1/10 to 1/3 of the measurement target; the standard recommends using an LPF of 1/20 to 1/10 of the BUJ PRBS baud rate.

An example setting prescribed by the existing CEI 3.0 standard when using a 28-Gbps PRBS31 signal as the measurement target Data signal is described below. Since the measurement target is 28 Gbps, the required baud rate is from 1/10 to 1/3 of this, or from 2.8 Gbps to 9.3 Gbps; since the LPF is 1/20 to 1/10 of the BUJ baud rate, the value is set from 140 MHz to 930 MHz. Moreover, the BUJ PRBS is selected from 7, 9 or 11 stages. If PRBS 7 stages is used as the measurement target signal, it is better to use either 9 or 11 stages for the BUJ instead of using the same PRBS pattern as the measurement target.

The following table 2.3.1 shows the range of baud rate settings when applying BUJ using the MP1900A.

Table 2.3.1 BUJ Settings

Table 2.3.2 MP1900A BUJ Baud Rate Setting Range

Using the previous example, BUJ baud rate for 28 Gbps is from 2.8 Gbps to 9.3 Gbps, the highest baud rate for BUJ is 6.25 Gbps. In this case, the standard specifies a setting range from 312.5 MHz to 625 MHz for the LPF.    Since the MP1900A LPF used for BUJ can be selected from 500 MHz, 300 MHz, 200 MHz, 100 MHz, and 50 MHz. 500 MHz should be selected in this example. Although the BUJ pattern can be selected from any of 7, 9, 11, 15, 23, and 31 when using the MP1900A, either 7, 9, or 11 is selected based on the CEI 3.0 standard.

• Half Period Jitter (F/2 Jitter)

With the recent speed increases in semiconductor bit rates, semiconductor vendors are avoiding deployment of hard-to-handle full-rate-clocks in semiconductor devices and are instead using a Selector at the final output stage and there are increasing numbers of examples using a half-rate clock (Figure 2.4.1).

If the half-rate clock does not have a Duty of 50% at this time, the output Data cycle looks as shown in Figure 2.4.3 and the narrow and wide state is repeated at each bit. This is called Half Period Jitter (HPJ).

The factors causing the Clock Duty change are a drift in the Clock Buffer Threshold voltage in the semiconductor device as well as distortion in the Clock waveform which can be caused by inadequate bandwidth as well as other issues.

Half Period Jitter is used to confirm whether or not a signal that is output under these conditions can be received correctly by the receiver circuit.

Since the MP1900A has a function for applying HPJ on the Pulse Pattern Generator (PPG) output, it can be used to add HPJ while applying jitter types such as SJ, RJ, BUJ to create even more severe stress conditions. In determining the HPJ setting amount, to separate-out DJ (DDPWS) caused by ISI, it is first necessary to generate a 1010 Clock pattern as the Data signal, which is defined as HPJ, and then to calibrate the DJ.